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ML145403 ML145404
ML145405 ML145408
Drivers/Receivers
RS 232/EIA-232-E and CCITT V.28
Legacy Device: Motorola MC145403, MC145404, MC145405, MC145408
These devices are silicon gate CMOS ICs that combine both the transmitter and receiver to fulfill the electrical specifications of EIA Standard 232-E and CCITT V .28. The drivers feature true TTL input compatibility, slew rate limiting outputs, 300 power-off source impedance, and output typically switching to within 25% of the supply rails. The receivers can handle up to 25 V while presenting 3 to 7 k impedance. Hysteresis in the receivers aid in the reception of noisy signals. By combining both drivers and receivers in a single CMOS chip, these devices provide efficient, low-power solutions for both EIA-232-E and V applications. .28 These devices offer the following performance features: * Operating Temperature Range TA = -40 to +85C Drivers * 5 to 12 V Supply Range * 300 Power-Off Source Impedance * Output Current Limiting * TTL and CMOS Compatible Inputs * Driver Slew Rate Range Limited to 30 V/s Maximum Receivers * 25 V Input Range * 3 to 7 k Input Impedance * 0.8 V of Hysteresis for Enhanced Noise Immunity * TTL and CMOS Compatible Outputs
Available Driver/Receiver Combinations
Device ML145403 ML145404 ML145405 ML145408 Drivers 3 4 5 5 Receivers 5 4 3 5 Figure 1 2 3 4 No. of Pins 20 20 20 24
Note: Lansdale lead free (Pb) product, as it becomes available, will be identified by a part number prefix change from ML to MLE.
Alternative EIA-232 devices to consider are: Three Supply ML145406 (3 x 3) Single Supply ML145407 (3 x 3)
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ML145403, ML145404, ML145405, ML145408
PIN ASSIGNMENTS (DIP AND SOG) ML145403 3 DRIVERS/5 RECEIVERS
VDD Rx1 Tx1 Rx2 Rx3 Tx2 Rx4 Rx5 Tx3 VSS 1 2 3 4 5 6 7 8 9 10 20 V CC R D R R D R R D 19 18 17 16 15 14 13 12 11 DO1 DI1 DO2 DO3 DI2 DO4 DO5 DI3 GND
LANSDALE Semiconductor, Inc.
ML145404 4 DRIVERS/4 RECEIVERS
VDD Rx1 Tx1 Rx2 Tx2 Rx3 Tx3 Rx4 Tx4 VSS 1 2 3 4 5 6 7 8 9 10 20 V CC R D R D R D R D 19 18 17 16 15 14 13 12 11 DO1 DI1 DO2 DI3 DO3 DI3 DO4 DI4 GND
ML145405 5 DRIVERS/3 RECEIVERS
VDD Rx1 Tx1 Tx2 Rx2 Tx3 Tx4 Rx3 Tx5 VSS 1 2 3 4 5 6 7 8 9 10 20 V CC R D D R D D R D 19 18 17 16 15 14 13 12 11 DO1 DI1 DI2 DO2 DI3 DI4 DO3 DI5 GND
ML145408 5 DRIVERS/5 RECEIVERS
VDD Rx1 Tx1 Rx2 Tx2 Rx3 Tx3 Rx4 Tx4 Rx5 Tx5 VSS 1 2 3 4 5 6 7 8 9 10 11 12 R D R D R D R D R D 24 V CC 23 22 21 20 19 18 17 16 15 14 13 DO1 DI1 DO2 DI2 DO3 DI3 DO4 DI4 DO5 DI5 GND
FUNCTIONAL DIAGRAM RECEIVER
ESD PROTECTION 15 k Rx 5.4 k VSS 1.0 V 1.8 V VSS + DO - Tx VDD VCC 300 VDD VCC LEVEL SHIFT ++ - - 1.4 V DI
DRIVER
VCC
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Issue A
LANSDALE Semiconductor, Inc.
ML145403, ML145404, ML145405, ML145408
ABSOLUTE MAXIMUM RATINGS
(Voltages referenced to GND, except where noted) Rating DC Supply Voltage (VDD VCC) Symbol VDD VSS VCC VIR Rx1 - Rxn DI1 - DIn DC Current Drain per Pin Power Dissipation Operating Temperature Range Storage Temperature Range I PD TA Tstg VSS - 15 to VDD + 15 0.5 to VCC + 15 00 1 - 40 to + 85 - 85 to + 150 mA W C C Value - 0.5 to + 13.5 + 0.5 to - 13.5 - 0.5 to + 6.0 Unit V This device contains circuitry to protect the inputs and outputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation it is recommended that Vout and Vin be constrained to the ranges described as follows: Digital I/O: Driver Inputs (DI): (GND VDI VCC). Receiver Outputs (DO): (GND VDO VCC). EIA-232 I/O: Driver Outputs (Tx): (VSS VTx1 - Txn VDD). Receiver Inputs (Rx): VSS - 15 V VRx1 - Rxn VDD + 15 V). Reliability of operation is enhanced if unused outputs are tied off to an appropriate logic voltage level (e.g., either GND or VCC for DI, and GND for Rx).
Input Voltage Range
V
DC ELECTRICAL CHARACTERISTICS (All polarities referenced to GND = 0 V, TA = - 40 to + 85C)
Parameter DC Supply Voltage Symbol VDD VSS VCC VDD = + 12 V VSS = - 12 V VCC = + 5 V IDD ISS ICC Min 4.5 - 4.5 4.5 -- -- -- Typ 5 to 12 - 5 to - 12 5 425 - 400 110 Max 13.2 - 13.2 5.5 635 - 600 200 Unit V
Quiescent Supply Current (Outputs Unloaded, Inputs Low)
A
RECEIVER ELECTRICAL SPECIFICATIONS
(Voltage polarities referenced to GND = 0 V, VDD = + 12 V, VSS = - 12 V, TA = - 40 to + 85C, VCC = + 5 V, 10%) Characteristic Input Turn-On Threshold VDO = VOL Input Turn-Off Threshold VDO = VOH Input Threshold Hysteresis = Von - Voff Input Resistance (VSS - 15 V) V Rx1 - Rxn (VDD + 15 V) High Level Output Voltage VRx = - 3 to - 25 V* (DO1 - DOn) Low Level Output Voltage VRx = + 3 to + 25 V* (DO1 - DOn) Iout = - 20 A Iout = - 1.0 mA Iout = + 2 mA Iout = + 4 mA Rx1 - Rxn Rx1 - Rxn Symbol Von Voff Vhys Rin VOH VOL Min 1.35 0.75 0.6 3 4.9 3.8 -- -- Typ 1.8 1 0.8 5.4 4.9 4.3 0.02 0.5 Max 2.35 1.25 -- 7 -- -- 0.5 0.7 Unit V V V k V V
* This is the range of input voltages as specified by EIA-232-E to cause a receiver to be in the high or low.
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ML145403, ML145404, ML145405, ML145408
LANSDALE Semiconductor, Inc.
DRIVER ELECTRICAL SPECIFICATIONS
(Voltage Polarities Referenced to GND = 0 V, VDD = + 12 V, VSS = - 12 V, TA = - 40 to + 85C, VCC = + 5 V, 10%) Characteristic Digital Input Voltage Logic 0 Logic 1 Input Current VDI = GND VDI = VCC Output High Voltage VDI = Logic 0, RL = 3 k VDD = + 5.0 V, VSS = - 5.0 V VDD = + 6.0 V, VSS = - 6.0 V VDD = + 12.0 V, VSS = - 12.0 V Output Low Voltage* VDI = Logic 1, RL = 3 k VDD = + 5.0 V, VSS = - 5.0 V VDD = + 6.0 V, VSS = - 6.0 V VDD = + 12.0 V, VSS = - 12.0 V Input Current (Figure 5) Output Short Circuit Current VDD = + 12 V, VSS = - 12 V Tx Shorted to GND** Tx Shorted to 15 V*** DI1 - DIn VIL VIH DI1 - DIn IIL IIH Tx1 - Txn VOH 3.5 4.3 9.2 Tx1 - Txn VOL -4 - 4.5 - 10 Tx1 - Txn Tx1 - Txn Zoff ISC -- -- 22 60 60 100 300 - 4.3 - 5.2 - 10.3 -- -- -- -- -- 3.9 4.7 9.5 -- -- -- V -- -- 7 -- -- 1.0 V -- 2 -- -- 0.8 -- A Symbol Min Typ Max Unit V
mA
* Voltage specifications are in terms of absolute values. ** Specification is for one Tx output pin to be shorted at a time. Should all three driver outputs be shorted simultaneously, device power dissipation limits will be exceeded. *** This condition could exceed package limitations.
SWITCHING CHARACTERISTICS (VCC = + 5 V, 10%, VDD = + 12 V, VSS = - 12 V, TA = - 40 to + 85C; See Figures 2 and 3)
Characteristic Symbol Min Typ Max Unit
Drivers
Propagation Delay Time Tx Low-to-High RL = 3 k, CL = 50 pF High-to-Low RL = 3 k, CL = 50 pF Output Slew Rate Minimum Load RL = 7 k, CL = 0 pF (VDD = 6 to 12 V, VSS = - 6 to - 12 V) Maximum Load RL = 3 k, CL = 2500 pF (VDD = 12 V, VSS = - 12 V, VCC = 5 V) tPLH -- tPHL -- SR -- 4 6 -- 30 -- 700 1000 V/s 500 1000 ns
Receivers (CL = 50 pF)
Propagation Delay Time Low-to-High High-to-Low Output Rise Time Output Fall Time tPLH -- tPHL tr tf -- -- -- 360 130 250 40 610 610 400 100 ns ns ns
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Issue A
LANSDALE Semiconductor, Inc.
ML145403, ML145404, ML145405, ML145408
22 20 18 16 14
24 VDD VCC 3 DI1 Tx1 DI2 DI3 DI4 DI5 VDD 12 Tx2 Tx3 Tx4 Tx5 GND 13 5 7 9 11 R out V in I Vin = 2 V
1
Figure 1. Power-Off Source Resistance Illustrated for ML145408
DRIVERS +3V DI 50% 0V tf Tx tPHL RECEIVERS +3V Rx 50% 0V tPHL 90% DO 10% tf tr tPLH VOH VOL Tx 90% 10% tPLH DRIVERS +3V -3V tSHL Slew Rate = 6V tSLH or tSHL +3V -3V tSLH VOL tr VOH
Figure 2. Switching Characteristics
Figure 3. Slew Rate Characteristics
PIN DESCRIPTIONS VCC Digital Power Supply The digital supply pin, which is connected to the logic power supply (+ 5.5 V maximum). GND Ground Ground return pin is typically connected to the signal ground pin of the EIA-232-E connector (Pin 7) as well as to the logic power supply ground. VDD Most Positive Device Pin The most positive power supply pin, which is typically + 5 to + 12 V .
VSS Most Negative Device Pin The most negative power supply pin, which is typically - 5 to - 12 V . Rx1 - Rxn Receive Data Input Pins These are the EIA-232-E receive signal inputs. A voltage between + 3 and + 25 V is decoded as a space, and causes the corresponding DO pin to swing to ground (0 V). A voltage between - 3 and - 25 V is decoded as a mark, and causes the corresponding DO pin to swing to VCC. DO1 - DOn Data Output Pins These are the receiver digital output pins which swing fromVCC to GND. Each output pin is capable of driving one LSTTL input load.
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Issue A
ML145403, ML145404, ML145405, ML145408
LANSDALE Semiconductor, Inc.
DI1 - DIn Data Input Pins These are the high impedance digital input pins to the drivers. Input voltage levels on these pins are LSTTL compatible and must be between VCC and GND. A weak pull-up on each input sets all unused DI pins to VCC, causing the corresponding unused driver outputs to be at VSS. Tx1 - TXn Transmit Data Output Pins These are the EIA-232-E transmit signal output pins, which swing from VDD to VSS. A logic 1 at the DI input causes the corresponding Tx output to swing to VSS. A logic 0 at the DI input causes the corresponding Tx out to swing to VDD. The actual levels and slew rate achieved will depend on the output loading (RL//CL). LEGACY APPLICATION INFORMATION POWER SUPPLY CONSIDERATIONS Figure 4 shows a technique to guard against excessive device current. The diode D1 prevents excessive current from flowing through an internal diode from the VCC pin to the VDD pinwhen VDD < VCC by approximately 0.6 V or greater. This high current condition can exist for a short period of time during power up/down. Additionally, if the + 12 V supply is
MMBZ15VDLT1 x 10
switched off while the + 5 V is on and the off supply is a low impedance to ground, the diode D1 will prevent current flow through the internal diode. The diode D2 is used as a voltage clamp, to prevent VSS from drifting positive to VCC, in the event that power is removed from VSS (Pin 12). If VSS power is removed, and the impedance from the VSS pin to ground is greater than approximately 3 k, this pin will be pulled to VCC by internal circuitry causing excessive current in the VCC pin. If by design, neither of the above conditions are allowed to exist, then the diodes D1 and D2 are not required. ESD PROTECTION - CAUTION ESD protection on IC devices that have their pins accessible to the outside world is essential. High static voltages applied to the pins when someone touches them either directly or in directly can cause damage to gate oxides and transistor junctions by coupling a portion of the energy from the I/O pin to the power supply buses of the IC. This coupling will usually occur through the internal ESD protection diodes. The key to protecting the IC is to shunt as much of the energy to ground as possible before it enters the IC. Figure 4 shows a technique which will clamp the ESD voltage at approximately 15 V using the MMBZ15VDLT1. Any residual voltage which appears on the supply pins is shunted to ground through the capacitors C1 - C3. This scheme has provided protection to the interface part up to 10kV, using the human body model test.
+ 12 V D1 C1 1N4001 Rx1 Tx1 Rx2 Tx2 Rx3 Tx3 Rx4 Tx4 Rx5 Tx5 C3 VSS 2 3 4 5 D 6 7 8 9 10 11 12 D2 - 12 V 1N5818 R D R D R D 19 DO3 18 DI3 17 DO4 16 DI4 15 DO5 14 DI5 13 GND R R D 23 DO1 22 DI1 21 DO2 20 DI2 1N4001 VDD 1 +5V 24 VCC C2
Figure 4.
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Issue A
LANSDALE Semiconductor, Inc.
ML145403, ML145404, ML145405, ML145408
OUTLINE DIMENSIONS
P DIP 20 = RP (ML145403RP, ML145404RP, ML145405RP) PLASTIC DIP CASE 738-03 -A20 11 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. DIM A B C D E F G J K L M N INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 15 0 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0 15 1.01 0.51
B
1 10
C
L
-TSEATING PLANE
K M E G F D 20 PL 0.25 (0.010)
M
N J 20 PL 0.25 (0.010) TA
M
M
T
B
M
P DIP 24 = LP (ML145408LP) PLASTIC DIP CASE 724-03 -A-
24 1 13 NOTES: 1. CHAMFERED CONTOUR OPTIONAL. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 4. CONTROLLING DIMENSION: INCH.
-B-
12
C -T-
SEATING PLANE
L
K E G F D
24 PL
NOTE 1
N J
24 PL
M
0.25 (0.010)
M
M
TB
M
0.25 (0.010)
TA
M
DIM A B C D E F G J K L M N
INCHES MIN MAX 1.230 1.265 0.250 0.270 0.145 0.175 0.015 0.020 0.050 BSC 0.040 0.060 0.100 BSC 0.007 0.012 0.110 0.140 0.300 BSC 0 15 0.020 0.040
MILLIMETERS MIN MAX 31.25 32.13 6.35 6.85 3.69 4.44 0.38 0.51 1.27 BSC 1.02 1.52 2.54 BSC 0.18 0.30 2.80 3.55 7.62 BSC 0 15 0.51 1.01
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Issue A
ML145403, ML145404, ML145405, ML145408
LANSDALE Semiconductor, Inc.
OUTLINE DIMENSIONS
SO 20W = -6P (ML145403-6P, ML145404-6P, ML145405-6P) SOG PACKAGE CASE 751D-04
11
-A-
20
-B-
1 10
10X
P 0.010 (0.25)
M
B
M
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 12.65 12.95 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0 7 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.499 0.510 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0 7 0.395 0.415 0.010 0.029
20X
D
M
0.010 (0.25)
TA
S
B
J
S
F R C -T-
18X SEATING PLANE X 45
G
K
M
-A-
24 13
SO 24W = -6P (ML145408-6P) SOG PACKAGE CASE 751E-04
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 15.25 15.54 7.40 7.60 2.35 2.65 0.35 0.49 0.41 0.90 1.27 BSC 0.23 0.32 0.13 0.29 0 8 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.601 0.612 0.292 0.299 0.093 0.104 0.014 0.019 0.016 0.035 0.050 BSC 0.009 0.013 0.005 0.011 0 8 0.395 0.415 0.010 0.029
-B-
12X
P 0.010 (0.25)
M
B
M
1
12
24X
D 0.010 (0.25)
M
J TA
S
B
S
F R C -T-
SEATING PLANE X 45
M
22X
G
K
DIM A B C D F G J K M P R
Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. "Typical" parameters which may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by the customer's technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc.
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